In dynamic random access memory (DRAM) integrated circuit devices, a DRAM cell array is typically arranged in rows and columns such that a particular DRAM cell is addressed by specifying its row and column within the array. A wordline connects a row of cells to a set of bitline sense amplifiers that detect the data in the cells. In a read operation, a subset of the data in the bitline sense amplifiers is then chosen, or “column-selected” for output. DRAM cells are “dynamic” in the sense that the stored data, typically in the form of charged and discharged storage capacitors, will dissipate after a relatively short period of time. Thus, in order to retain the information, the contents of the DRAM cells must be refreshed. The charged or discharged state of the storage capacitor must be reapplied to an individual memory cell in a repetitive manner. The maximum amount of time allowable between refreshing operations is determined by the charge storage capabilities of the storage capacitors that make up the DRAM cell array. DRAM manufacturers typically specify a refresh time for which it guarantees data retention in the DRAM cells.
A refresh operation is similar to a read operation, but no data is output. The sensing of the data in the cells by the bitline sense amplifiers is followed by a restoring operation that results in the data being rewritten to the cells. The data is, thus, “refreshed”. The refresh operation is performed by enabling a wordline according to a row address, and enabling a bitline sense amplifier. In addition, the refresh operation may be carried out by operating the bitline sense amplifier without receiving an external refresh address. In this case, a refresh address counter, which is integrated in a DRAM device chip, generates a row address subsequent to receiving an external refresh command. It is well known that DRAM cells are refreshed by self-refresh function to retain stored data. The self-refresh function is one of performing refresh operations automatically within the DRAM when in a “standby” mode to retain the data written in its memory cells.
In low power DRAM devices for mobile applications, power consumption during a standby or sleep mode is critical. A major portion of power consumption during the standby or sleep mode is for refresh operation to retain data. Hence, the key for power reduction during the standby or sleep mode is to reduce the refresh frequency. In low power DRAM devices, one of the available power reduction features is a partial refresh that restricts refresh and self-refresh operation during the standby or sleep mode to a portion of the total memory array. This feature enables the device to reduce refresh current by refreshing only that part of the memory array required by a host system. That technique is a “partial array refresh” that supports array selections of ¼ array, ½ array or ¾ array with fixed array location. For example, a partial array self-refresh power-saving function with a low power extended mode register is known (see, for example, Micron® 256 Mb:x32, MOBILE SDRAM, data sheet).
In known partial array self-refresh scheme, a fixed and pre-determined partial array selection is performed as per mode register settings. It does not, thus, perform flexible combinations of array selection for power saving. In DRAM devices which are partitioned as “banks”, “subblocks” or “sub-arrays”, the bank, subblock or sub-array addresses are key performance factors to achieve faster accesses to partial array memories. It is a simple solution, without DRAM performance degradation, to limit partial array self-refresh feature in low power DRAM devices. Therefore, the fixed and pre-determined scheme is a good compromise between the power saving and the DRAM performance.
A simplified conventional DRAM device is shown in FIG. 1. Referring to FIG. 1 that shows an example DRAM device, a memory controller (not shown) provides it with commands and addresses for DRAM operation. The DRAM device has a full memory block consisting of four banks 112-0, 112-1, 112-2 and 112-3. An external command controller 121, which is synchronized with clocks, includes a command decoder that interprets the commands and generates a refresh request signal 123 indicating whether the memory blocks are to be refreshed or not. The commands include EMRS (extended mode register set) commands. When the EMRS commands are fed to the external command controller 121, an EMRS signal 125 is provided by the command decoder thereof.
An extended mode register 131 writes information carried on selection addresses “A[0:2]” therein in accordance with mode register set commands BA[0:1]. The selection addresses “A[0:2]” give instructions for the partial array self-refresh (PASR) configuration. Once the PASR configuration information is written into the extended mode register 131, it provides a PASR signal 133, the bits of which indicate whether “full array” should be refreshed or partial array should be refreshed in the self-refresh mode. In response to the refresh request signal 123 and the PASR signal 133, an internal bank address counter 135 generates an internal bank address signal 137 containing internal bank addresses that are fed to a multiplexer 141.
Also, the mode register set commands BA[0:1] are latched by an external bank address latch 143. In accordance with the latched addresses, the external bank address latch 143 provides an external bank address signal 145 containing external bank addresses to the multiplexer 141. The multiplexer 141 selects the internal bank addresses or the external bank addresses in response to the refresh request signal 123.
In response to “1” or “0” of the refresh request signal 123, the multiplexer 141 selects the internal bank addresses of the internal bank address signal 137 or the external bank addresses of the external bank address signal 145. The selected addresses are fed to a bank address decoder 151 which in turn provides a decoded address signal 153 to the full memory block consisting of four banks 112-0, 112-1, 112-2 and 112-3. The decoded address signal 153 contains four bank select signals 154-0, 154-1, 154-2 and 154-3. Therefore, the bank address decoder 151 enables one of the four bank select signals 154-0, 154-1, 154-2 and 154-3.
In accordance with the mode register set commands BA[0:1] and the selection addresses “A[0:2]”, the banks are designated as shown in following Table 1:
TABLE 1A[2]A[1]A[0]Banks to be Self-Refreshed000Four Banks001Two Banks (e.g., Bank [0] and [1)010One Bank (e.g., Bank [0])
In the DRAM device shown in FIG. 1, the PASR supports only the array selections of ¼ array (i.e., one bank), ½ array (i.e., two banks) or ¾ array (i.e., three banks) with fixed array location. The DRAM device has ability to save power consumption in the self-refresh mode, however it lacks of controllability of selecting which memory bank will be retained in the self-refresh mode. Such a low power DRAM design with the EMRS function allows a full memory array, a half memory array or a ¼ memory array to be selected. When a ¼ memory array is selected for self-refresh mode, for example, the DRAM device enables least significant banks for the selection of a ¼ memory. It may not, thus, be possible to select the other memory banks for specific data retention. It may also not be possible to select another combination of banks, for example bank [0] and bank [3], for the self-refresh mode.